The invention relates to the field of high speed networking applications, and more particularly, to the field of RAM buffer controllers which control the address ports to random access memory to make the memory appear to be operating as two independent FIFOs.
There are three main application areas for high speed networking systems. The first is in back end networks where the network is used for interconnecting a variety of storage devices such as disks and tape drives with the host computers' backplane. Usually data transfers between disks and CPUs in such configurations call for extremely high throughput. A second application for high speed networks is high performance front end networks wherein a number of computers, terminals, and other devices are connected together by a single transmission medium over which messages are sent between the units on the network. A third application area is in backbone networks where lower speed networks are connected together by high speed networks that act as bridges between the low speed networks. High throughput capability is needed to prevent bottlenecks.
In such networks, a host system, which can be a computer, a terminal, a peripheral, or some other device, utilizes a specially adapted system for interface between the host system and the transmission media. Such systems normally include encoders and decoders for transforming the data into the proper signal format for transmission media and media access controllers for taking care of contentions for the media by different host systems. The host system is connected to a buffer memory by a RAM buffer controller and a data path controller. The purpose of the buffer memory is to store messages which are to be transmitted until such time as they are transmitted, and to store messages that have been received until such time as the host system is able to retrieve them from memory and process them. The data path controller controls the data inputs of the memory while the RAM buffer controller controls the address inputs of the memory.
In such systems, it is useful to have the buffer memory controlled in such a manner that it simulates the operation of a FIFO memory. This allows the host system to store messages to be transmitted in the buffer memory in a particular order, and allows the message to be transmitted in the same order. The same is true for received messages, i.e., the received message will be stored in buffer memory in a particular order and will be read out of the buffer by the host system in the same order.
There are existing FIFO RAM controllers which are available in the form of integrated circuits. One such circuit is the Signetics 8X60 which manages the address pins of standard off-the-shelf RAMs in such a manner that the RAMs implement a high speed/high capacity FIFO stack. Another such system is the Xilinx Inc. logic cell array in the form of a printer buffer controller model no. XC2064, described in Electronic Design of Nov. 14, 1985 at page 139. Both of these RAM controllers cause standard off-the-shelf RAM to implement a single FIFO buffer.
Unfortunately, neither of these systems has sufficient flexibility and performance in terms of architectural capability to support a complex high speed network application. For example, neither system can cause a single bank of memory to implement two independently operating FIFOs. Further, prior art FIFO RAM controllers generally use counters to keep track of the read and write pointer locations. Such counters cannot generally be initialized to random, desired addresses when any of the other counters are in use in controlling the address applied to the address pins of the controlled memory. The ability to independently set any pointer in the system while another pointer is being used to control the address pins is a useful feature in that it provides great flexibility to the system software designers.
Further, such prior art systems do not generally support random access to any location in memory which access is not constrained by FIFO address limitations. It is useful in implementing various control functions to have a random access capability such that the contents of any address in the memory can be read or changed regardless of whether it is outside currently established FIFO starting or ending addresses.
Another shortcoming of the prior art FIFO controllers is in the area of flushing packets or data which has arrived but which has proven to be not desirable for retention in the memory. Such data may be data which is not addressed to the host system or which may have a transmission error destroying the integrity of the data. The prior art systems do not provide circuitry which allows flushing of data in simple and expeditious fashion.
It is also useful when managing a FIFO to be able to record status and length information associated with each packet in a memory location adjacent to the location as opposed to storing it at the end of the packet. The best location for such status and length information is in the memory location just preceding the first byte of the packet data. Unfortunately the prior art systems do not provide circuitry which adequately supports the ability to simply and quickly write status and length information in the memory location just preceding the first byte of the received packet data.
It is also useful when managing a FIFO to be able to abort a particular packer for some reason without losing its status and length information. The prior art systems do not provide circuitry which easily supports such a control function.
In some networking applications such as token ring networks, it is desirable to be able to transmit data bytes, words, or packets in linked list format, i.e., where the bytes, words, packets to be transmitted are not stored in contiguous locations in memory but instead are spread throughout the memory. Such a linked list has a pointer at the end of each member of the list which points to the starting address for the next member of the list. The prior art systems do not have circuitry which allows linked lists of data to be transmitted. Typically such prior art systems use counters which are incremented by a clock such that the pointers for transmission of data vary continuously from one memory location to the next memory location in contiguous fashion. Such an architecture cannot be easily adapted to linked list transmission.
It is very useful in management of FIFOs to be able to establish flexible starting and ending addresses for the FIFO. The registers which are used to store such starting addresses and ending addresses are not used in linked list transmission. This is because linked list transmission is not a FIFO operation so starting and ending addresses are meaningless. However, during linked list transmission there sometimes arises a need to save the current read address pointer in the middle of transmitting a particular linked list and change the read address pointer to a fixed predetermined address to begin transmitting a particular packet which starts at that address. Such a situation typically arises when, in a token ring situation, a ring recovery packet must be transmitted because of a problem on the network. It is useful to be able to utilize the memory locations which store the starting address and ending address for FIFO operations as new link and save registers for use in vectoring transmission to the starting address of the recovery packet and for saving the current contents of the read pointer.
Finally, it is also useful to be able to send packets in back-to-back fashion with virtually no time between the end of transmission of a first packet and the beginning of transmission of a second packet. Sometimes in FIFO management by a FIFO controller, there are simultaneous access requests by various units in the network interface. For example, the host system may request access to the memory for purposes for storing therein a packet to be transmitted. For such a transaction, the FIFO controller must provide the memory with a write pointer to provide an address into which the first byte of data from the host system will be written. Simultaneously, a packet of data addressed to the host system may be arriving from another system on the network. Such a packet must be stored in the memory as it arrives. In the prior art systems where two FIFO buffers cannot be simultaneously managed, such a situation can never occur, and if it does occur, an error condition will exist. However in systems where such a situation can occur, it will be necessary to arbitrate the simultaneous requests to determine the then current highest priority request. Then, it is useful to have the arbitration occur in a pipelined fashion such that the arbitration is occurring simultaneously with service of the prior request. That is, it is useful to be able to arbitrate a first group of requests and then service the winning request simultaneously with concurrent arbitration with a second group of requests such that upon completion of the service of the winning request from the first arbitration, the service of the winning request from the second arbitration may begin immediately.
Thus a need has arisen for a flexible system for managing external memory so as to provide simultaneous independent FIFO implementation and to satisfy all the above noted needs.